One approach to a SRAM cell is to use two coupled CMOS inverters (which is similar to an NMOS cell but with the load transistors in the NMOS cell replaced with PMOS transistors). The CMOS cell will require more area but the power consumption when the circuit is quiescent will be virtually eliminated. One method to improve the packing density of CMOS SRAMs is to stack the transistors one on top of another. This arrangement allows the circuit design to extend into the third dimension.
Low stand-by power and high speed operation are key factors for the next generation of SRAMs. In addition, high packing density SRAMs exhibit serious soft error problems under high speed operation. The storage node voltage tends to drop as the operation speed is increased. This voltage drop can allow alpha particles to cause soft errors.